Institutionen för systemteknik (ISY)

In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex-6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices.

In this work, a processing architecture for grant-free machine type communication based on compressive sensing is proposed. The architecture can be adapted for a number of parameters. An instantiation for 128 terminals and 96 antennas is implemented. Without memories it consumes 1.52 W and occupies and area of 5.1 mm(2) in a 28 nm SOI CMOS process. The implemented instance can process about 10k messages per second, each containing four bits.

Many contemporary FPGAs have introduced a pre-adder before the hard multipliers, primarily aimed at linear-phase FIR filters. In this work, structural modifications are proposed with the aim of reducing the LUT resource utilization and, finally, using the pre-adder for implementing single path delay feedback pipeline FFTs. The results show that two thirds of the LUT resources can be saved when the pre-adder has bypass functionality, as in the Xilinx 6 and 7 series, compared to a direct mapping.

When generating a sine table to be used in, e.g., frequency synthesis circuits, a widely used way to assign the table content is to simply take a sine wave with the desired amplitude and quantize it using rounding.This results in uncontrolled rounding of up to 0.5 LSB, causing some noise.In this paper we present a method for increasing the signal quality, simply by adjust the amplitude within a ±0.5 range from the intended. This will not affect the maximum value of the sinusoid, but can increase the spurious free dynamic range with some dB.